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 @article{memory_wall,  
 title={Hitting the memory wall: implications of the obvious}, 
 url={http://dx.doi.org/10.1145/216585.216588}, 
 DOI={10.1145/216585.216588}, 
 journal={ACM SIGARCH Computer Architecture News}, 
 author={Wulf, Wm. A. and McKee, Sally A.}, 
 year={1995}, 
 month={Mar}, 
 pages={20–24}, 
 language={en-US} 
 }
@misc{intel_i7_13700k,
  author = {Intel},
  title = {Intel Core i7-13700K Processor - Specifications},
  year = {2024},
  howpublished = {\url{https://www.intel.cn/content/www/cn/zh/products/sku/230500/intel-core-i713700k-processor-30m-cache-up-to-5-40-ghz/specifications.html}},
  note = {Accessed: 2024-04-10}
}
 @inproceedings{Young_Chishti_Qureshi_2019,  
 title={TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems}, 
 url={http://dx.doi.org/10.1109/iccd46524.2019.00055}, 
 DOI={10.1109/iccd46524.2019.00055}, 
 booktitle={2019 IEEE 37th International Conference on Computer Design (ICCD)}, 
 author={Young, Vinson and Chishti, Zeshan A. and Qureshi, Moinuddin K.}, 
 year={2019}, 
 month={Nov}, 
 language={en-US} 
 }

  @inproceedings{Loh_Hill_2011,  
 title={Efficiently enabling conventional block sizes for very large die-stacked DRAM caches}, 
 url={http://dx.doi.org/10.1145/2155620.2155673}, 
 DOI={10.1145/2155620.2155673}, 
 booktitle={Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture}, 
 author={Loh, Gabriel H. and Hill, Mark D.}, 
 year={2011}, 
 month={Dec}, 
 language={en-US} 
 }
  @article{Chaudhuri_Agrawal_Gaur_Subramoney_2017,  
 title={Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches}, 
 volume={14}, 
 url={http://dx.doi.org/10.1145/3046680}, 
 DOI={10.1145/3046680}, 
 number={1}, 
 journal={ACM Transactions on Architecture and Code Optimization}, 
 author={Chaudhuri, Mainak and Agrawal, Mukesh and Gaur, Jayesh and Subramoney, Sreenivas}, 
 year={2017}, 
 month={Mar}, 
 pages={1–29}, 
 language={en-US} 
 }
 @article{Zhang_Sui_Hou_Zhang_2021,  
 title={Line-Coalescing DRAM Cache}, 
 url={http://dx.doi.org/10.1016/j.suscom.2020.100449}, 
 DOI={10.1016/j.suscom.2020.100449}, 
 journal={Sustainable Computing: Informatics and Systems}, 
 author={Zhang, Qianlong and Sui, Xiufeng and Hou, Rui and Zhang, Lixin}, 
 year={2021}, 
 month={Mar}, 
 pages={100449}, 
 language={en-US} 
 }
  @article{locality_Denning_2005,  
 title={The locality principle}, 
 volume={48}, 
 url={http://dx.doi.org/10.1145/1070838.1070856}, 
 DOI={10.1145/1070838.1070856}, 
 number={7}, 
 journal={Communications of the ACM}, 
 author={Denning, Peter J.}, 
 year={2005}, 
 month={Jul}, 
 pages={19–24}, 
 language={en-US} 
 }

 @misc{amd_ryzen_7_5800x3d,
  author = {AMD},
  title = {AMD Ryzen 7 5800X3D - Product Specifications},
  year = {2022},
  howpublished = {\url{https://www.amd.com/zh-cn/products/processors/desktops/ryzen/amd-ryzen-7-5800x3d.html#product-specs}},
  note = {Accessed: 2024-04-10}
}

@book{hennessy2011computer,
  title={Computer architecture: a quantitative approach},
  author={Hennessy, John L and Patterson, David A},
  year={2011},
  publisher={Elsevier}
}

 @article{gem5_2011,  
 title={The gem5 simulator}, 
 url={http://dx.doi.org/10.1145/2024716.2024718}, 
 DOI={10.1145/2024716.2024718}, 
 journal={ACM SIGARCH Computer Architecture News}, 
 author={Binkert, Nathan and Beckmann, Bradford and Black, Gabriel and Reinhardt, Steven K. and Saidi, Ali and Basu, Arkaprava and Hestness, Joel and Hower, Derek R. and Krishna, Tushar and Sardashti, Somayeh and Sen, Rathijit and Sewell, Korey and Shoaib, Muhammad and Vaish, Nilay and Hill, Mark D. and Wood, David A.}, 
 year={2011}, 
 month={May}, 
 pages={1–7}, 
 language={en-US} 
 }

 @article{Gober_The_Championship_Simulator_2022,
author = {Gober, Nathan and Chacon, Gino and Wang, Lei and Gratz, Paul V. and Jimenez, Daniel A. and Teran, Elvira and Pugsley, Seth and Kim, Jinchun},
doi = {10.48550/arXiv.2210.14324},
title = {{The Championship Simulator: Architectural Simulation for Education and Competition}},
year = {2022}
}

@inproceedings{qemu_2005,
author = {Bellard, Fabrice},
title = {QEMU, a fast and portable dynamic translator},
year = {2005},
publisher = {USENIX Association},
address = {USA},
abstract = {We present the internals of QEMU, a fast machine emulator using an original portable dynamic translator. It emulates several CPUs (x86, PowerPC, ARM and Sparc) on several hosts (x86, PowerPC, ARM, Sparc, Alpha and MIPS). QEMU supports full system emulation in which a complete and unmodified operating system is run in a virtual machine and Linux user mode emulation where a Linux process compiled for one target CPU can be run on another CPU.},
booktitle = {Proceedings of the Annual Conference on USENIX Annual Technical Conference},
pages = {41},
numpages = {1},
location = {Anaheim, CA},
series = {ATEC '05}
}

@ARTICLE{chipyard_2020,
  author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar, Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanović, Krste and Nikolić, Borivoje},
  journal={IEEE Micro}, 
  title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs}, 
  year={2020},
  volume={40},
  number={4},
  pages={10-21},
  keywords={Generators;Open source software;Computational modeling;IP networks;Hardware;Physical design;Computer architecture},
  doi={10.1109/MM.2020.2996616}}

@INPROCEEDINGS{micro2022xiangshan,
  author={Xu, Yinan and Yu, Zihao and Tang, Dan and Chen, Guokai and Chen, Lu and Gou, Lingrui and Jin, Yue and Li, Qianruo and Li, Xin and Li, Zuojun and Lin, Jiawei and Liu, Tong and Liu, Zhigang and Tan, Jiazhan and Wang, Huaqiang and Wang, Huizhe and Wang, Kaifan and Zhang, Chuanqi and Zhang, Fawang and Zhang, Linjuan and Zhang, Zifei and Zhao, Yangyang and Zhou, Yaoyang and Zhou, Yike and Zou, Jiangrui and Cai, Ye and Huan, Dandan and Li, Zusong and Zhao, Jiye and Chen, Zihao and He, Wei and Quan, Qiyuan and Liu, Xingwu and Wang, Sa and Shi, Kan and Sun, Ninghui and Bao, Yungang},
  booktitle={2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)},
  title={{Towards Developing High Performance RISC-V Processors Using Agile Methodology}},
  year={2022},
  volume={},
  number={},
  pages={1178-1199},
  doi={10.1109/MICRO56248.2022.00080}
}

@Article{xiangshan_2022,
title = {香山开源高性能RISC-V处理器设计与实现},
journal = {计算机研究与发展},
volume = {60},
number = {3},
pages = {476-493},
year = {2023},
issn = {1000-1239},
doi = {10.7544/issn1000-1239.202221036},
url = {https://crad.ict.ac.cn/cn/article/doi/10.7544/issn1000-1239.202221036},
author = {王凯帆 and 徐易难 and 余子濠 and 唐丹 and 陈国凯 and 陈熙 and 勾凌睿 and 胡轩 and 金越 and 李乾若 and 李昕 and 蔺嘉炜 and 刘彤 and 刘志刚 and 王华强 and 王诲喆 and 张传奇 and 张发旺 and 张林隽 and 张紫飞 and 张梓悦 and 赵阳洋 and 周耀阳 and 邹江瑞 and 蔡晔 and 郇丹丹 and 李祖松 and 赵继业 and 何伟 and 孙凝晖 and 包云岗}
}
%====================



  @inproceedings{Abella_González_2006,  
 title={Heterogeneous way-size cache}, 
 url={http://dx.doi.org/10.1145/1183401.1183436}, 
 DOI={10.1145/1183401.1183436}, 
 booktitle={Proceedings of the 20th annual international conference on Supercomputing}, 
 author={Abella, Jaume and González, Antonio}, 
 year={2006}, 
 month={Jun}, 
 language={en-US} 
 }
  @inproceedings{Bobbala_Salvatierra_Lee_2010,  
 title={Composite Pseudo-Associative Cache for Mobile Processors}, 
 url={http://dx.doi.org/10.1109/mascots.2010.49}, 
 DOI={10.1109/mascots.2010.49}, 
 booktitle={2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems}, 
 author={Bobbala, Lakshmi Deepika and Salvatierra, Javier and Lee, Byeong Kil}, 
 year={2010}, 
 month={Aug}, 
 language={en-US} 
 }

  @article{Qureshi_Thompson_Patt_2005,  
 title={The V-Way Cache: Demand Based Associativity via Global Replacement}, 
 volume={33}, 
 url={http://dx.doi.org/10.1145/1080695.1070015}, 
 DOI={10.1145/1080695.1070015}, 
 number={2}, 
 journal={ACM SIGARCH Computer Architecture News}, 
 author={Qureshi, Moinuddin K. and Thompson, David and Patt, Yale N.}, 
 year={2005}, 
 month={May}, 
 pages={544–555}, 
 language={en-US} 
 }

  @inproceedings{Sanchez_Kozyrakis_2010,  
 title={The ZCache: Decoupling Ways and Associativity}, 
 url={http://dx.doi.org/10.1109/micro.2010.20}, 
 DOI={10.1109/micro.2010.20}, 
 booktitle={2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture}, 
 author={Sanchez, Daniel and Kozyrakis, Christos}, 
 year={2010}, 
 month={Dec}, 
 language={en-US} 
 }

  @inproceedings{Seznec_2002,  
 title={Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio}, 
 url={http://dx.doi.org/10.1109/isca.1994.288133}, 
 DOI={10.1109/isca.1994.288133}, 
 booktitle={Proceedings of 21 International Symposium on Computer Architecture}, 
 author={Seznec, A.}, 
 year={2002}, 
 month={Dec}, 
 language={en-US} 
 }

  @article{Albonesi_1999,  
 title={Selective cache ways: on-demand cache resource allocation}, 
 journal={International Symposium on Microarchitecture,International Symposium on Microarchitecture}, 
 author={Albonesi, DavidH.}, 
 year={1999}, 
 month={Nov}, 
 language={en-US} 
 }

  @inproceedings{Chiou_Jain_Rudolph_Devadas_2000,  
 title={Application-specific memory management for embedded systems using software-controlled caches}, 
 url={http://dx.doi.org/10.1145/337292.337523}, 
 DOI={10.1145/337292.337523}, 
 booktitle={Proceedings of the 37th conference on Design automation  - DAC ’00}, 
 author={Chiou, Derek and Jain, Prabhat and Rudolph, Larry and Devadas, Srinivas}, 
 year={2000}, 
 month={Jan}, 
 language={en-US} 
 }
%============
 @inproceedings{Kim_Burger_Keckler_2002,  
 title={An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches}, 
 url={http://dx.doi.org/10.1145/605397.605420}, 
 DOI={10.1145/605397.605420}, 
 booktitle={Proceedings of the 10th international conference on Architectural support for programming languages and operating systems}, 
 author={Kim, Changkyu and Burger, Doug and Keckler, Stephen W.}, 
 year={2002}, 
 month={Oct}, 
 language={en-US} 
 }
  @inproceedings{Beckmann_Marty_Wood_2006,  
 title={ASR: Adaptive Selective Replication for CMP Caches}, 
 url={http://dx.doi.org/10.1109/micro.2006.10}, 
 DOI={10.1109/micro.2006.10}, 
 booktitle={2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’06)}, 
 author={Beckmann, Bradford and Marty, Michael and Wood, David}, 
 year={2006}, 
 month={Dec}, 
 language={en-US} 
 }

  @inproceedings{Merino_Puente_Gregorio_2010,  
 title={ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture}, 
 url={http://dx.doi.org/10.1109/hpca.2010.5416641}, 
 DOI={10.1109/hpca.2010.5416641}, 
 booktitle={HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture}, 
 author={Merino, Javier and Puente, Valentin and Gregorio, Jose A}, 
 year={2010}, 
 month={Jan}, 
 language={en-US} 
 }
  @inproceedings{Chaudhuri_2009,  
 title={PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches}, 
 url={http://dx.doi.org/10.1109/hpca.2009.4798258}, 
 DOI={10.1109/hpca.2009.4798258}, 
 booktitle={2009 IEEE 15th International Symposium on High Performance Computer Architecture}, 
 author={Chaudhuri, Mainak}, 
 year={2009}, 
 month={Feb}, 
 language={en-US} 
 }
  @article{Beckmann_Sanchez_2013,  
 title={Jigsaw: scalable software-defined caches}, 
 journal={International Conference on Parallel Architectures and Compilation Techniques,International Conference on Parallel Architectures and Compilation Techniques}, 
 author={Beckmann, Nathan and Sanchez, Daniel}, 
 year={2013}, 
 month={Oct}, 
 language={en-US} 
 }

  @inproceedings{ Zhang_Sadayappan_2008,  
 title={Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems}, 
 url={http://dx.doi.org/10.1109/hpca.2008.4658653}, 
 DOI={10.1109/hpca.2008.4658653}, 
 booktitle={2008 IEEE 14th International Symposium on High Performance Computer Architecture}, 
 author={ Jiang Lin and  Qingda Lu and  Xiaoning Ding and  Zhao Zhang and  Xiaodong Zhang and Sadayappan, P.}, 
 year={2008}, 
 month={Feb}, 
 language={en-US} 
 }

  @inproceedings{Zhang_Dwarkadas_Shen_2009,  
 title={Towards practical page coloring-based multicore cache management}, 
 url={http://dx.doi.org/10.1145/1519065.1519076}, 
 DOI={10.1145/1519065.1519076}, 
 booktitle={Proceedings of the 4th ACM European conference on Computer systems}, 
 author={Zhang, Xiao and Dwarkadas, Sandhya and Shen, Kai}, 
 year={2009}, 
 month={Apr}, 
 language={en-US} 
 }
  @inproceedings{Jin_Chen_Wang_Wang_Wen_Luo_Li_2009,  
 title={A Simple Cache Partitioning Approach in a Virtualized Environment}, 
 url={http://dx.doi.org/10.1109/ispa.2009.47}, 
 DOI={10.1109/ispa.2009.47}, 
 booktitle={2009 IEEE International Symposium on Parallel and Distributed Processing with Applications}, 
 author={Jin, Xinxin and Chen, Haogang and Wang, Xiaolin and Wang, Zhenlin and Wen, Xiang and Luo, Yingwei and Li, Xiaoming}, 
 year={2009}, 
 month={Jan}, 
 language={en-US} 
 }

  @inproceedings{Tsai_Beckmann_Sanchez_2017,  
 title={Jenga: Software-Defined Cache Hierarchies}, 
 url={http://dx.doi.org/10.1145/3079856.3080214}, 
 DOI={10.1145/3079856.3080214}, 
 booktitle={Proceedings of the 44th Annual International Symposium on Computer Architecture}, 
 author={Tsai, Po-An and Beckmann, Nathan and Sanchez, Daniel}, 
 year={2017}, 
 month={Jun}, 
 language={en-US} 
 }

 @ARTICLE{9839561,
  author={Berger, Deanna and Jacobi, Christian and Walters, Craig R. and Sonnelitter, Robert J. and Cadigan, Mike and Klein, Matthias},
  journal={IEEE Micro}, 
  title={Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability}, 
  year={2023},
  volume={43},
  number={1},
  pages={58-66},
  keywords={Pipelines;System-on-chip;Random access memory;Wires;Optimization;Low latency communication},
  doi={10.1109/MM.2022.3193642}}
@INPROCEEDINGS{hbm_2014,
  author={Joonyoung Kim and Younsu Kim},
  booktitle={2014 IEEE Hot Chips 26 Symposium (HCS)}, 
  title={HBM: Memory solution for bandwidth-hungry processors}, 
  year={2014},
  volume={},
  number={},
  pages={1-24},
  keywords={Memory management;Bandwidth;Servers;Graphics;Random access memory;Program processors},
  doi={10.1109/HOTCHIPS.2014.7478812}}

@inproceedings{Salehian_Yan_2017,  
 title={Evaluation of Knight Landing High Bandwidth Memory for HPC Workloads}, 
 url={http://dx.doi.org/10.1145/3149704.3149766}, 
 DOI={10.1145/3149704.3149766}, 
 booktitle={Proceedings of the Seventh Workshop on Irregular Applications: Architectures and Algorithms}, 
 author={Salehian, Solmaz and Yan, Yonghong}, 
 year={2017}, 
 month={Nov}, 
 language={en-US} 
 }

@inproceedings{Unison_cache_2014,  
 title={Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache}, 
 url={http://dx.doi.org/10.1109/micro.2014.51}, 
 DOI={10.1109/micro.2014.51}, 
 booktitle={2014 47th Annual IEEE/ACM International Symposium on Microarchitecture}, 
 author={Jevdjic, Djordje and Loh, Gabriel H. and Kaynak, Cansu and Falsafi, Babak}, 
 year={2014}, 
 month={Dec}, 
 language={en-US} 
 }

 @inproceedings{Jang_Lee_Kim_Kim_Kim_Jeong_Lee_2016,  
 title={Efficient footprint caching for Tagless DRAM Caches}, 
 url={http://dx.doi.org/10.1109/hpca.2016.7446068}, 
 DOI={10.1109/hpca.2016.7446068}, 
 booktitle={2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)}, 
 author={Jang, Hakbeom and Lee, Yongjun and Kim, Jongwon and Kim, Youngsok and Kim, Jangwoo and Jeong, Jinkyu and Lee, Jae W.}, 
 year={2016}, 
 month={Mar}, 
 language={en-US} 
 }
 @inproceedings{Lee_Kim_Jang_Yang_Kim_Jeong_Lee_2015,  
 title={A fully associative, tagless DRAM cache}, 
 url={http://dx.doi.org/10.1145/2749469.2750383}, 
 DOI={10.1145/2749469.2750383}, 
 booktitle={Proceedings of the 42nd Annual International Symposium on Computer Architecture}, 
 author={Lee, Yongjun and Kim, Jongwon and Jang, Hakbeom and Yang, Hyunggyun and Kim, Jangwoo and Jeong, Jinkyu and Lee, Jae W.}, 
 year={2015}, 
 month={Jun}, 
 language={en-US} 
 }
  @inproceedings{Qureshi_Loh_2012,  
 title={Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design}, 
 url={http://dx.doi.org/10.1109/micro.2012.30}, 
 DOI={10.1109/micro.2012.30}, 
 booktitle={2012 45th Annual IEEE/ACM International Symposium on Microarchitecture}, 
 author={Qureshi, Moinuddin K. and Loh, Gabe H.}, 
 year={2012}, 
 month={Dec}, 
 language={en-US} 
 }
  @inproceedings{Jevdjic_Volos_Falsafi_2013,  
 title={Die-stacked DRAM caches for servers: hit ratio, latency, or bandwidth? have it all with footprint cache}, 
 url={http://dx.doi.org/10.1145/2485922.2485957}, 
 DOI={10.1145/2485922.2485957}, 
 booktitle={Proceedings of the 40th Annual International Symposium on Computer Architecture}, 
 author={Jevdjic, Djordje and Volos, Stavros and Falsafi, Babak}, 
 year={2013}, 
 month={Jun}, 
 language={en-US} 
 }
  @inproceedings{Sim_Loh_Kim_OConnor_Thottethodi_2012,  
 title={A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch}, 
 url={http://dx.doi.org/10.1109/micro.2012.31}, 
 DOI={10.1109/micro.2012.31}, 
 booktitle={2012 45th Annual IEEE/ACM International Symposium on Microarchitecture}, 
 author={Sim, Jaewoong and Loh, Gabriel H. and Kim, Hyesoon and OConnor, Mike and Thottethodi, Mithuna}, 
 year={2012}, 
 month={Dec}, 
 language={en-US} 
 }

  @inproceedings{Knyaginin_Papaefstathiou_Stenstrom_2018,  
 title={ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness}, 
 url={http://dx.doi.org/10.1109/hpca.2018.00022}, 
 DOI={10.1109/hpca.2018.00022}, 
 booktitle={2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)}, 
 author={Knyaginin, Dmitry and Papaefstathiou, Vassilis and Stenstrom, Per}, 
 year={2018}, 
 month={Feb}, 
 language={en-US} 
 }
  @inproceedings{Ramos_Gorbatov_Bianchini_2011,  
 title={Page placement in hybrid memory systems}, 
 url={http://dx.doi.org/10.1145/1995896.1995911}, 
 DOI={10.1145/1995896.1995911}, 
 booktitle={Proceedings of the international conference on Supercomputing}, 
 author={Ramos, Luiz E. and Gorbatov, Eugene and Bianchini, Ricardo}, 
 year={2011}, 
 month={May}, 
 language={en-US} 
 }
 @INPROCEEDINGS{7324725,
  author={Chen, An},
  booktitle={2015 45th European Solid State Device Research Conference (ESSDERC)}, 
  title={Emerging nonvolatile memory (NVM) technologies}, 
  year={2015},
  volume={},
  number={},
  pages={109-113},
  keywords={Nonvolatile memory;Switches;Random access memory;Phase change materials;Performance evaluation;Magnetic tunneling;Computer architecture;nonvolatile memory;storage;memory hierarchy;architecture;selectors;neuromorphics;security},
  doi={10.1109/ESSDERC.2015.7324725}}

  @article{Chen2016ARO,
  title={A review of emerging non-volatile memory (NVM) technologies and applications},
  author={An Chen},
  journal={Solid-state Electronics},
  year={2016},
  volume={125},
  pages={25-38},
  url={https://api.semanticscholar.org/CorpusID:99193577}
}

@article{yang2020exploring,
  title={Exploring performance characteristics of the optane 3d xpoint storage technology},
  author={Yang, Jinfeng and Li, Bingzhe and Lilja, David J},
  journal={ACM Transactions on Modeling and Performance Evaluation of Computing Systems (TOMPECS)},
  volume={5},
  number={1},
  pages={1--28},
  year={2020},
  publisher={ACM New York, NY, USA}
}
 @inproceedings{Chou_Jaleel_Qureshi_2017,  
 title={BATMAN: techniques for maximizing system bandwidth of memory systems with stacked-DRAM}, 
 url={http://dx.doi.org/10.1145/3132402.3132404}, 
 DOI={10.1145/3132402.3132404}, 
 booktitle={Proceedings of the International Symposium on Memory Systems}, 
 author={Chou, Chiachen and Jaleel, Aamer and Qureshi, Moinuddin}, 
 year={2017}, 
 month={Oct}, 
 language={en-US} 
 }

  @inproceedings{Chou_Jaleel_Qureshi_2014,  
 title={CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache}, 
 url={http://dx.doi.org/10.1109/micro.2014.63}, 
 DOI={10.1109/micro.2014.63}, 
 booktitle={2014 47th Annual IEEE/ACM International Symposium on Microarchitecture}, 
 author={Chou, Chia Chen and Jaleel, Aamer and Qureshi, Moinuddin K.}, 
 year={2014}, 
 month={Dec}, 
 language={en-US} 
 }

  @inproceedings{Meswani_Blagodurov_Roberts_Slice_Ignatowski_Loh_2015,  
 title={Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories}, 
 url={http://dx.doi.org/10.1109/hpca.2015.7056027}, 
 DOI={10.1109/hpca.2015.7056027}, 
 booktitle={2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)}, 
 author={Meswani, Mitesh R. and Blagodurov, Sergey and Roberts, David and Slice, John and Ignatowski, Mike and Loh, Gabriel H.}, 
 year={2015}, 
 month={Feb}, 
 language={en-US} 
 }
  @inproceedings{Prodromou_Meswani_Jayasena_Loh_Tullsen_2017,  
 title={MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories}, 
 url={http://dx.doi.org/10.1109/hpca.2017.39}, 
 DOI={10.1109/hpca.2017.39}, 
 booktitle={2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)}, 
 author={Prodromou, Andreas and Meswani, Mitesh and Jayasena, Nuwan and Loh, Gabriel and Tullsen, Dean M.}, 
 year={2017}, 
 month={Feb}, 
 language={en-US} 
 }
  @inproceedings{Ryoo_Meswani_Prodromou_John_2017,  
 title={SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization}, 
 url={http://dx.doi.org/10.1109/hpca.2017.20}, 
 DOI={10.1109/hpca.2017.20}, 
 booktitle={2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)}, 
 author={Ryoo, Jee Ho and Meswani, Mitesh R. and Prodromou, Andreas and John, Lizy K.}, 
 year={2017}, 
 month={Feb}, 
 language={en-US} 
 }
 @inproceedings{Sim_Alameldeen_Chishti_Wilkerson_Kim_2014,  
 title={Transparent Hardware Management of Stacked DRAM as Part of Memory}, 
 url={http://dx.doi.org/10.1109/micro.2014.56}, 
 DOI={10.1109/micro.2014.56}, 
 booktitle={2014 47th Annual IEEE/ACM International Symposium on Microarchitecture}, 
 author={Sim, Jaewoong and Alameldeen, Alaa R. and Chishti, Zeshan and Wilkerson, Chris and Kim, Hyesoon}, 
 year={2014}, 
 month={Dec}, 
 language={en-US} 
 }

  @article{Bloom_1970,  
 title={Space/time trade-offs in hash coding with allowable errors}, 
 url={http://dx.doi.org/10.1145/362686.362692}, 
 DOI={10.1145/362686.362692}, 
 journal={Communications of the ACM}, 
 author={Bloom, Burton H.}, 
 year={1970}, 
 month={Jul}, 
 pages={422–426}, 
 language={en-US} 
 }
  @inproceedings{Salapura_Blumrich_Gara_2008,  
 title={Design and implementation of the blue gene/P snoop filter}, 
 url={http://dx.doi.org/10.1109/hpca.2008.4658623}, 
 DOI={10.1109/hpca.2008.4658623}, 
 booktitle={2008 IEEE 14th International Symposium on High Performance Computer Architecture}, 
 author={Salapura, Valentina and Blumrich, Matthias and Gara, Alan}, 
 year={2008}, 
 month={Feb}, 
 language={en-US} 
 }
 @article{conway2010cache,
  title={Cache hierarchy and memory subsystem of the AMD Opteron processor},
  author={Conway, Pat and Kalyanasundharam, Nathan and Donley, Gregg and Lepak, Kevin and Hughes, Bill},
  journal={IEEE micro},
  volume={30},
  number={2},
  pages={16--29},
  year={2010},
  publisher={IEEE}
}

  @inproceedings{Nori_Gaur_Rai_Subramoney_Wang_2018,  
 title={Criticality aware tiered cache hierarchy: a fundamental relook at multi-level cache hierarchies}, 
 url={http://dx.doi.org/10.1109/isca.2018.00019}, 
 DOI={10.1109/isca.2018.00019}, 
 booktitle={2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)}, 
 author={Nori, Anant Vithal and Gaur, Jayesh and Rai, Siddharth and Subramoney, Sreenivas and Wang, Hong}, 
 year={2018}, 
 month={Jun}, 
 language={en-US} 
 }

  @inproceedings{Moshovos_Memik_Falsafi_Choudhary_2002,  
 title={JETTY: filtering snoops for reduced energy consumption in SMP servers}, 
 url={http://dx.doi.org/10.1109/hpca.2001.903254}, 
 DOI={10.1109/hpca.2001.903254}, 
 booktitle={Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture}, 
 author={Moshovos, A. and Memik, G. and Falsafi, B. and Choudhary, A.}, 
 year={2002}, 
 month={Nov}, 
 language={en-US} 
 }
  @inproceedings{Salapura_Blumrich_Gara_2007,  
 title={Improving the accuracy of snoop filtering using stream registers}, 
 url={http://dx.doi.org/10.1145/1327171.1327174}, 
 DOI={10.1145/1327171.1327174}, 
 booktitle={Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture}, 
 author={Salapura, Valentina and Blumrich, Matthias and Gara, Alan}, 
 year={2007}, 
 month={Sep}, 
 language={en-US} 
 }
  @article{Ferdman_Adileh_Kocberber_Volos_Alisafaee_Jevdjic_Kaynak_Popescu_Ailamaki_Falsafi_2011,  
 title={Clearing the Clouds: A Study of Emerging Workloads on Modern Hardware}, 
 author={Ferdman, Michael and Adileh, Almutaz and Kocberber, Onur and Volos, Stavros and Alisafaee, Mohammad and Jevdjic, Djordje and Kaynak, Cansu and Popescu, Adrian and Ailamaki, Anastasia and Falsafi, Babak}, 
 year={2011}, 
 month={Jan}, 
 language={en-US} 
 }
  @article{Faldu_Diamond_Grot_2020,  
 title={Domain-Specialized Cache Management for Graph Analytics}, 
 journal={arXiv: Distributed, Parallel, and Cluster Computing,arXiv: Distributed, Parallel, and Cluster Computing}, 
 author={Faldu, Priyank and Diamond, Jeff and Grot, Boris}, 
 year={2020}, 
 month={Jan}, 
 language={en-US} 
 }
  @article{Hameed_Bauer_Henkel_2013,  
 title={Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies}, 
 journal={Compilers, Architecture, and Synthesis for Embedded Systems,Compilers, Architecture, and Synthesis for Embedded Systems}, 
 author={Hameed, Fazal and Bauer, Lars and Henkel, Jorg}, 
 year={2013}, 
 month={Sep}, 
 language={en-US} 
 }
  @article{Cha_Kim_Park_Huh_2019,  
 title={Morphable DRAM Cache Design for Hybrid Memory Systems}, 
 volume={16}, 
 url={http://dx.doi.org/10.1145/3338505}, 
 DOI={10.1145/3338505}, 
 number={3}, 
 journal={ACM Transactions on Architecture and Code Optimization}, 
 author={Cha, Sanghoon and Kim, Bokyeong and Park, Chang Hyun and Huh, Jaehyuk}, 
 year={2019}, 
 month={Sep}, 
 pages={1–24}, 
 language={en-US} 
 }

  @inproceedings{Huang_Nagarajan_2014,  
 title={ATCache: reducing DRAM cache latency via a small SRAM tag cache}, 
 url={http://dx.doi.org/10.1145/2628071.2628089}, 
 DOI={10.1145/2628071.2628089}, 
 booktitle={Proceedings of the 23rd international conference on Parallel architectures and compilation}, 
 author={Huang, Cheng-Chieh and Nagarajan, Vijay}, 
 year={2014}, 
 month={Aug}, 
 language={en-US} 
 }

  @inproceedings{Hameed_Bauer_Henkel_2014,  
 title={Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture}, 
 url={http://dx.doi.org/10.1145/2593069.2593197}, 
 DOI={10.1145/2593069.2593197}, 
 booktitle={Proceedings of the 51st Annual Design Automation Conference}, 
 author={Hameed, Fazal and Bauer, Lars and Henkel, Jörg}, 
 year={2014}, 
 month={Jun}, 
 language={en-US} 
 }
  @inproceedings{Vasilakis_Papaefstathiou_Trancoso_Sourdis_2020,  
 title={Hybrid2: Combining Caching and Migration in Hybrid Memory Systems}, 
 url={http://dx.doi.org/10.1109/hpca47549.2020.00059}, 
 DOI={10.1109/hpca47549.2020.00059}, 
 booktitle={2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)}, 
 author={Vasilakis, Evangelos and Papaefstathiou, Vassilis and Trancoso, Pedro and Sourdis, Ioannis}, 
 year={2020}, 
 month={Feb}, 
 language={en-US} 
 }

@INPROCEEDINGS{Li_Gao,
  author={Li, Yiwei and Gao, Mingyu},
  booktitle={2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)}, 
  title={Baryon: Efficient Hybrid Memory Management with Compression and Sub-Blocking}, 
  year={2023},
  volume={},
  number={},
  pages={137-151},
  keywords={Costs;Nonvolatile memory;Memory management;Layout;Systems architecture;Data compression;Bandwidth;Hybrid memory;compression;sub-blocking},
  doi={10.1109/HPCA56546.2023.10071115}
  }

  @inproceedings{Sanchez_Kozyrakis_2013,  
 title={ZSim}, 
 url={http://dx.doi.org/10.1145/2485922.2485963}, 
 DOI={10.1145/2485922.2485963}, 
 booktitle={Proceedings of the 40th Annual International Symposium on Computer Architecture}, 
 author={Sanchez, Daniel and Kozyrakis, Christos}, 
 year={2013}, 
 month={Jun}, 
 language={en-US} 
 }
 @INPROCEEDINGS{8342082,
  author={Tonetto, Rafael Billig and Nazar, Gabriel L. and Beck, Antonio Carlos Schneider},
  booktitle={2018 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, 
  title={Precise evaluation of the fault sensitivity of OoO superscalar processors}, 
  year={2018},
  volume={},
  number={},
  pages={613-616},
  keywords={Program processors;Hardware;Resilience;Sensitivity;Registers;Checkpointing;Circuit faults;Fault injection;superscalar processor;register-transfer level},
  doi={10.23919/DATE.2018.8342082}
}

 @article{Owahid_John_2019,  
 title={Wasted dynamic power and correlation to instruction set architecture for CPU throttling}, 
 url={http://dx.doi.org/10.1007/s11227-018-2637-6}, 
 DOI={10.1007/s11227-018-2637-6}, 
 journal={The Journal of Supercomputing}, 
 author={Owahid, Abdullah A. and John, Eugene B.}, 
 year={2019}, 
 month={May}, 
 pages={2436–2454}, 
 language={en-US} 
 }

 @techreport{ARM2021,
  author = {{ARM Limited}},
  title = {AMBA AXI Protocol Specification},
  institution = {ARM Limited},
  year = {2021},
  type = {Technical Report},
  note = {Version IHI0022H.c},
  url = {https://developer.arm.com/documentation/ihi0022/k/?lang=en}
}
@techreport{TileLink2020,
  author = {SiFive, Inc.},
  title = {TileLink Specification Version 1.8.1},
  institution = {SiFive, Inc.},
  year = {2020},
  month = {January},
  note = {Version 1.8.1},
  url = {https://starfivetech.com/uploads/tilelink_spec_1.8.1.pdf}
}
@techreport{ARM2024CHI,
  author = {ARM Limited},
  title = {AMBA CHI Architecture Specification},
  institution = {ARM Limited},
  year = {2024},
  month = {March},
  type = {Technical Report},
  version = {IHI0050G},
  note = {Ninth public release},
  url = {https://developer.arm.com/documentation/ihi0050/g/?lang=en}
}
 @inproceedings{Zhao_Iyer_Makineni_Newell_Cheng_2010,  
 title={NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies}, 
 url={http://dx.doi.org/10.1145/1787275.1787314}, 
 DOI={10.1145/1787275.1787314}, 
 booktitle={Proceedings of the 7th ACM international conference on Computing frontiers}, 
 author={Zhao, Li and Iyer, Ravi and Makineni, Srihari and Newell, Don and Cheng, Liqun}, 
 year={2010}, 
 month={May}, 
 language={en-US} 
 }

  @inproceedings{Yan_Sprabery_Gopireddy_Fletcher_Campbell_Torrellas_2019,  
 title={Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World}, 
 url={http://dx.doi.org/10.1109/sp.2019.00004}, 
 DOI={10.1109/sp.2019.00004}, 
 booktitle={2019 IEEE Symposium on Security and Privacy (SP)}, 
 author={Yan, Mengjia and Sprabery, Read and Gopireddy, Bhargava and Fletcher, Christopher and Campbell, Roy and Torrellas, Josep}, 
 year={2019}, 
 month={May}, 
 language={en-US} 
 }

 @misc{SpinalHDL,
  title        = {SpinalHDL},
  author       = {Dolu1990 and contributors},
  year         = {2024},
  howpublished = {\url{https://github.com/SpinalHDL/SpinalHDL}},
  note         = {Accessed: 2024-04-15}
}

 @inproceedings{chisel,  
 title={Chisel}, 
 url={http://dx.doi.org/10.1145/2228360.2228584}, 
 DOI={10.1145/2228360.2228584}, 
 booktitle={Proceedings of the 49th Annual Design Automation Conference}, 
 author={Bachrach, Jonathan and Vo, Huy and Richards, Brian and Lee, Yunsup and Waterman, Andrew and Avižienis, Rimas and Wawrzynek, John and Asanović, Krste}, 
 year={2012}, 
 month={Jun}, 
 language={en-US} 
 }

  @inproceedings{Kokolis_Skarlatos_Torrellas_2019,  
 title={PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems}, 
 url={http://dx.doi.org/10.1109/hpca.2019.00012}, 
 DOI={10.1109/hpca.2019.00012}, 
 booktitle={2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)}, 
 author={Kokolis, Apostolos and Skarlatos, Dimitrios and Torrellas, Josep}, 
 year={2019}, 
 month={Feb}, 
 language={en-US} 
 }

 @inproceedings{Vasilakis_Papaefstathiou_Trancoso_Sourdis_2018,  
 title={FusionCache: Using LLC tags for DRAM cache}, 
 url={http://dx.doi.org/10.23919/date.2018.8342077}, 
 DOI={10.23919/date.2018.8342077}, 
 booktitle={2018 Design, Automation \&amp; Test in Europe Conference \&amp; Exhibition (DATE)}, 
 author={Vasilakis, Evangelos and Papaefstathiou, Vassilis and Trancoso, Pedro and Sourdis, Ioannis}, 
 year={2018}, 
 month={Mar}, 
 language={en-US} 
 }
 @inproceedings{Kanellopoulos_Nam_Bostanci_Bera_Sadrosadati_Kumar_Bartolini_Mutlu_2023,  
 title={Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources}, 
 url={http://dx.doi.org/10.1145/3613424.3614276}, 
 DOI={10.1145/3613424.3614276}, 
 booktitle={56th Annual IEEE/ACM International Symposium on Microarchitecture}, 
 author={Kanellopoulos, Konstantinos and Nam, Hong Chul and Bostanci, Nisa and Bera, Rahul and Sadrosadati, Mohammad and Kumar, Rakesh and Bartolini, Davide Basilio and Mutlu, Onur}, 
 year={2023}, 
 month={Oct}, 
 language={en-US} 
 }
@article{10.1145/3293447,
author = {Vasilakis, Evangelos and Papaefstathiou, Vassilis and Trancoso, Pedro and Sourdis, Ioannis},
title = {Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache},
year = {2019},
issue_date = {December 2018},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {15},
number = {4},
issn = {1544-3566},
url = {https://doi.org/10.1145/3293447},
doi = {10.1145/3293447},
journal = {ACM Trans. Archit. Code Optim.},
month = {jan},
articleno = {65},
numpages = {23},
keywords = {3D stacking, Caches, DRAM, memory, processor}
}
 @inproceedings{Dhar_Wang_Franke_Xiong_Huang_Hwu_Kim_Chen_2020,  
 title={FReaC Cache: Folded-logic Reconfigurable Computing in the Last Level Cache}, 
 url={http://dx.doi.org/10.1109/micro50266.2020.00021}, 
 DOI={10.1109/micro50266.2020.00021}, 
 booktitle={2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)}, 
 author={Dhar, Ashutosh and Wang, Xiaohao and Franke, Hubertus and Xiong, Jinjun and Huang, Jian and Hwu, Wen-mei and Kim, Nam Sung and Chen, Deming}, 
 year={2020}, 
 month={Oct}, 
 language={en-US} 
 }

   @inproceedings{Burcea_Somogyi_Moshovos_Falsafi_2008,  
 title={Predictor virtualization}, 
 url={http://dx.doi.org/10.1145/1346281.1346301}, 
 DOI={10.1145/1346281.1346301}, 
 booktitle={Proceedings of the 13th international conference on Architectural support for programming languages and operating systems}, 
 author={Burcea, Ioana and Somogyi, Stephen and Moshovos, Andreas and Falsafi, Babak}, 
 year={2008}, 
 month={Mar}, 
 language={en-US} 
 }

  @inproceedings{Pellegrini_2021,  
 title={Arm Neoverse N2: Arm’s 2nd generation high performance infrastructure CPUs and system IPs}, 
 url={http://dx.doi.org/10.1109/hcs52781.2021.9567483}, 
 DOI={10.1109/hcs52781.2021.9567483}, 
 booktitle={2021 IEEE Hot Chips 33 Symposium (HCS)}, 
 author={Pellegrini, Andrea}, 
 year={2021}, 
 month={Aug}, 
 language={en-US} 
 }

  @inproceedings{Qureshi_Patt_2006,  
 title={Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches}, 
 url={http://dx.doi.org/10.1109/micro.2006.49}, 
 DOI={10.1109/micro.2006.49}, 
 booktitle={2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’06)}, 
 author={Qureshi, Moinuddin and Patt, Yale}, 
 year={2006}, 
 month={Dec}, 
 language={en-US} 
 }
  @article{Kim_Chandra_Solihin_2004,  
 title={Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture}, 
 journal={International Conference on Parallel Architectures and Compilation Techniques,International Conference on Parallel Architectures and Compilation Techniques}, 
 author={Kim, Seongbeom and Chandra, D. and Solihin, Yan}, 
 year={2004}, 
 month={Sep}, 
 language={en-US} 
 }

 @article{ElSayed2018KPartAH,
  title={KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores},
  author={Nosayba El-Sayed and Anurag Mukkara and Po-An Tsai and Harshad Kasture and Xiaosong Ma and Daniel S{\'a}nchez},
  journal={2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)},
  year={2018},
  pages={104-117},
  url={https://api.semanticscholar.org/CorpusID:3154832}
}

@inproceedings{Xie2009PIPPPP,
  title={PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches},
  author={Yuejian Xie and Gabriel H. Loh},
  booktitle={International Symposium on Computer Architecture},
  year={2009},
  url={https://api.semanticscholar.org/CorpusID:14697515}
}
@article{Manikantan2012ProbabilisticSC,
  title={Probabilistic Shared Cache Management (PriSM)},
  author={R. Manikantan and Kaushik Rajan and Ramaswamy Govindarajan},
  journal={2012 39th Annual International Symposium on Computer Architecture (ISCA)},
  year={2012},
  pages={428-439},
  url={https://api.semanticscholar.org/CorpusID:1703725}
}
 @inproceedings{Sanchez_Kozyrakis_2011,  
 title={Vantage: scalable and efficient fine-grain cache partitioning}, 
 url={http://dx.doi.org/10.1145/2000064.2000073}, 
 DOI={10.1145/2000064.2000073}, 
 booktitle={Proceedings of the 38th annual international symposium on Computer architecture}, 
 author={Sanchez, Daniel and Kozyrakis, Christos}, 
 year={2011}, 
 month={Jun}, 
 language={en-US} 
 }
  @inproceedings{Wang_Chen_2014,  
 title={Futility Scaling: High-Associativity Cache Partitioning}, 
 url={http://dx.doi.org/10.1109/micro.2014.46}, 
 DOI={10.1109/micro.2014.46}, 
 booktitle={2014 47th Annual IEEE/ACM International Symposium on Microarchitecture}, 
 author={Wang, Ruisheng and Chen, Lizhong}, 
 year={2014}, 
 month={Dec}, 
 language={en-US} 
 }

  @inproceedings{Davanam_Lee_2010,  
 title={Towards Smaller-Sized Cache for Mobile Processors Using Shared Set-Associativity}, 
 url={http://dx.doi.org/10.1109/itng.2010.120}, 
 DOI={10.1109/itng.2010.120}, 
 booktitle={2010 Seventh International Conference on Information Technology: New Generations}, 
 author={Davanam, Naveen and Lee, Byeong Kil}, 
 year={2010}, 
 month={Jan}, 
 language={en-US} 
 }

  @article{Takayashiki_Sato_Komatsu_Kobayashi_2019,  
 title={A Skewed Multi-banked Cache for Many-core Vector Processors}, 
 volume={6}, 
 url={http://dx.doi.org/10.14529/jsfi190305}, 
 DOI={10.14529/jsfi190305}, 
 number={3}, 
 journal={Supercomputing Frontiers and Innovations}, 
 author={Takayashiki, Hikaru and Sato, Masayuki and Komatsu, Kazuhiko and Kobayashi, Hiroaki}, 
 year={2019}, 
 month={Sep}, 
 language={en-US} 
 }
  @inbook{Seznec_Bodin_1993,  
 title={Skewed-associative caches}, 
 url={http://dx.doi.org/10.1007/3-540-56891-3_24}, 
 DOI={10.1007/3-540-56891-3_24}, 
 booktitle={Lecture Notes in Computer Science,PARLE ’93 Parallel Architectures and Languages Europe}, 
 author={Seznec, André and Bodin, Francois}, 
 year={1993}, 
 month={Jan}, 
 pages={305–316}, 
 language={en-US} 
 }
 @inproceedings{Jaleel_Theobald_Steely_Emer_2010,  
 title={High performance cache replacement using re-reference interval prediction (RRIP)}, 
 url={http://dx.doi.org/10.1145/1815961.1815971}, 
 DOI={10.1145/1815961.1815971}, 
 booktitle={Proceedings of the 37th annual international symposium on Computer architecture}, 
 author={Jaleel, Aamer and Theobald, Kevin B. and Steely, Simon C. and Emer, Joel}, 
 year={2010}, 
 month={Jun}, 
 language={en-US} 
 }
  @article{Qureshi_Jaleel_Patt_Steely_Emer_2008,  
 title={Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching}, 
 url={http://dx.doi.org/10.1109/mm.2008.14}, 
 DOI={10.1109/mm.2008.14}, 
 journal={IEEE Micro}, 
 author={Qureshi, Moinuddin K. and Jaleel, Aamer and Patt, Yale N. and Steely, Simon C. and Emer, Joel}, 
 year={2008}, 
 month={Jan}, 
 pages={91–98}, 
 language={en-US} 
 }
 @article{Hamerly_Perelman_Lau_Calder_2005,  
 title={SimPoint 3.0: Faster and More Flexible Program Phase Analysis}, 
 journal={Journal of Instruction-level Parallelism,Journal of Instruction-level Parallelism}, 
 author={Hamerly, Greg and Perelman, Erez and Lau, Jeremy and Calder, Brad}, 
 year={2005}, 
 month={Jan}, 
 language={en-US} 
 }
%---------------------------------------------------------------------------%

%下面是开源处理器的

 @inproceedings{open_source,  
 title={A comparative survey of open-source application-class RISC-V processor implementations}, 
 url={http://dx.doi.org/10.1145/3457388.3458657}, 
 DOI={10.1145/3457388.3458657}, 
 booktitle={Proceedings of the 18th ACM International Conference on Computing Frontiers}, 
 author={Dörflinger, Alexander and Albers, Mark and Kleinbeck, Benedikt and Guan, Yejun and Michalik, Harald and Klink, Raphael and Blochwitz, Christopher and Nechi, Anouar and Berekovic, Mladen}, 
 year={2021}, 
 month={May}, 
 language={en-US} 
 }
 @misc{VexRiscv,
  title = {{VexRiscv: A FPGA friendly RISC-V CPU implementation using SpinalHDL}},
  author = {{SpinalHDL}},
  year = {2023},
  publisher = {GitHub},
  journal = {GitHub Repository},
  howpublished = {\url{https://github.com/SpinalHDL/VexRiscv}},
}

@misc{v_cores,
  title = {{CORE-V Cores: Open-source RISC-V cores}},
  author = {{OpenHW Group}},
  year = {2024},
  publisher = {GitHub},
  journal = {GitHub Repository},
  howpublished = {\url{https://github.com/openhwgroup/core-v-cores}},
  note = {Accessed: 2024-05-20}
}

 @inproceedings{Balkind,  
 title={OpenPiton}, 
 url={http://dx.doi.org/10.1145/2872362.2872414}, 
 DOI={10.1145/2872362.2872414}, 
 booktitle={Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems}, 
 author={Balkind, Jonathan and McKeown, Michael and Fu, Yaosheng and Nguyen, Tri and Zhou, Yanqi and Lavrov, Alexey and Shahrad, Mohammad and Fuchs, Adi and Payne, Samuel and Liang, Xiaohua and Matl, Matthew and Wentzlaff, David}, 
 year={2016}, 
 month={Mar}, 
 language={en-US} 
 }

 @manual{wbspec_b3,
  title        = {WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores},
  author       = {{OpenCores}},
  organization = {OpenCores},
  year         = 2010,
  month        = {September},
  note         = {Version B.3},
  url          = {https://cdn.opencores.org/downloads/wbspec_b3.pdf}
}

@manual{ocp_spec,
  title        = {Open Core Protocol (OCP) Specification},
  author       = {{Accellera Systems Initiative}},
  organization = {Accellera Systems Initiative},
  year         = 2024,
  note         = {Version 3.0},
  url          = {https://www.accellera.org/downloads/standards/ocp}
}